1. Field of the Invention
The invention relates to CMOS integrated circuits and, more specifically, to the protection of these circuits against the phenomenon of latch-up which may destroy certain parts of the CMOS integrated circuit.
CMOS technology gives rise to numerous parasitic structures with four layers PNPN. Although these P nor N regions are needed for the desired transistors, the combination of four successive P,N,P, and N layers produces a (undesired but operable) thyristor. As extensively discussed in the device literature, such a thyristor can be analyzed in terms of two parasitic bipolar transistors and associated series resistors.
A single unwanted pulse or an overvoltage on the supply may prompt the triggering of some of these thyristors: this is the phenomonen of latch-up of CMOS circuits.
2. Description of the Prior Art
The triggering of these parasitic thyristor structures sets up a variably sharp short-circuit which is generally destructive through the over-heating of the circuit. The standard way of preventing latch-up is to use very strict rules for the designing of the CMOS circuits. In particular:
to reduce the gain of the bipolar transistors, the width of their base is increased by giving the wells a substantial depth and by making the diffusions in the substrate at a distance from the wells;
to reduce the lateral resistance values, the substrate and well connectors are greatly increased in number.
The reduction of the lateral resistance values also serves to reduce the gain of the bipolar transistors (by the short-circuit of the emitter-base junction).
These rules entail very severe constraints and are very costly in terms of space with uncertain results in practice: for one circuit, they will give very good results and for another circuit they will give poor results.
In certain cases, it is preferred to use an epitaxial substrate instead of one that is uniformly doped in the bulk (a bulk substrate). The epitaxial substrate is highly enriched, for example with N.sup.+ doping, surmounted by a very fine epitaxial layer with low level N.sup.- doping. It can be used chiefly to reduce the lateral resistance values but this is a very costly technology for a result that is still not sure (because of the problem of the reproducibility of the result from one circuit to another).
Take a CMOS circuit. At two supply terminals, it receives a positive voltage Vcc, generally five volts in terms of nominal value, and a more negative (ground) voltage Vss, generally equal to zero volts. The CMOS circuit accepts a maximum voltage Vmax=Vcc-Vss, at its terminals, of the order of 7 volts. The immunity of the CMOS circuit to the latch-up phenomenon is defined by the over-voltage V1 and the external current I1 for which the latch-up is triggered. Typically, it is sought to have V1 greater than 2Vmax and the current I1 as high as possible. The above-described approaches can be used to have I1 of the order of 20 milliamperes. By the present invention, it is sought to take I1 to one hundred milliamperes. Thus, CMOS products will be obtained that are truly well protected against the latch-up phenomenon. Furthermore, it is sought to reduce both the cost of the protection in terms of the place occupied by the circuit and its cost price.
The invention starts with a standard technology CMOS circuit with limit parameters of immunization to latch-up (V1, I1) proper to the internal circuitry.
In the invention, a limiter component is interposed between the supply terminals, in parallel with the internal CMOS circuitry. This limiter component gets triggered for a voltage E at its terminals of less than V1 and consumes high current I.sub.e far higher than the current I1 for a voltage V1 at its terminals, i.e. this is a component with low equivalent resistance when it is triggered.
In the invention, the limiter component is integrated into the CMOS circuit. Thus, while the intensity of the external current needed to prompt the latch-up phenomenon in the internal circuitry remains unchanged (I1), by contrast the total external current I'1 to be given to the CMOS circuit, equal to I1 without the limiter, is increased in the invention by the current (Ie) flowing through the limiter. Thus, the apparent value I'1 of the external current for triggering the latch-up has been increased. This apparent value then depends on the sizing of the limiter.
In one improvement, the limiter is protected against electrostatic discharges.